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1 for more information www.linear.com/LT8330 typical a pplica t ion fea t ures descrip t ion low i q boost/sepic/ inverting converter with 1a, 60v switch the lt ? 8330 is a current mode dc/dc converter capable of generating either positive or negative output voltages using a single feedback pin. it can be configured as a boost, sepic or inverting converter consuming as low as 6a of quiescent current. low ripple burst mode opera - tion maintains high efficiency down to very low output currents while keeping the output ripple below 15 mv in a typical application. the internally compensated current mode architecture results in stable operation over a wide range of input and output voltages. integrated soft-start and frequency foldback functions are included to control inductor current during start-up. the 2mhz operation combined with small package options, enables low cost, area efficient solutions. 48v boost converter a pplica t ions n 3v to 40v input voltage range n ultralow quiescent current and low ripple burst mode ? operation: i q = 6a n 1a, 60v power switch n positive or negative output voltage programming with a single feedback pin n fixed 2mhz switching frequency n accurate 1.6v en/uvlo pin threshold n internal compensation and soft-start n low profile (1mm) thinsot? package n low profile (0.75mm) 8-lead (3mm 2mm) dfn package n industrial and automotive n telecom n medical diagnostic equipment n portable electronics l, lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. efficiency and power loss lt 8330 8330fa 0 10 20 30 40 50 60 70 80 90 efficiency 100 0 100 200 300 400 500 600 700 800 power loss 900 1000 efficiency (%) power loss (mw) 8330 ta01b 4.7f 34.8k 4.7f 1f 4.7pf load current (ma) v in sw fbx gnd en/uvlo LT8330 v in 12v 6.8h v out 48v 135ma v cc 0 int 1m 40 80 120 160
2 for more information www.linear.com/LT8330 a bsolu t e maxi m u m r a t ings sw ............................................................................ 60 v v in , en / uvlo ............................................................ 40 v en / u vlo pin above v in pin ........................................ 6 v intv cc ( note 2) .......................................................... 4 v fbx ........................................................................... 4 v (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range LT8330es6#pbf LT8330es6#trpbf ltgmq 6-lead plastic tsot-23 C40c to 125c LT8330is6#pbf LT8330is6#trpbf ltgmq 6-lead plastic tsot-23 C40c to 125c LT8330hs6#pbf LT8330hs6#trpbf ltgmq 6-lead plastic tsot-23 C40c to 150c LT8330eddb#pbf LT8330eddb#trpbf lgrc 8-lead (3mm 2mm) plastic dfn C40c to 125c LT8330iddb#pbf LT8330iddb#trpbf lgrc 8-lead (3mm 2mm) plastic dfn C40c to 125c LT8330hddb#pbf LT8330hddb#trpbf lgrc 8-lead (3mm 2mm) plastic dfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking , go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. top view 9 ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1fbx nc sw sw en/uvlo intv cc v in gnd ja = 60c/w exposed pad (pin 9) is gnd, must be soldered to pcb 1 2 3 6 5 4 top view s6 package 6-lead plastic tsot-23 v in intv cc en/uvlo sw gnd fbx ja = 125c/w, jc = 102c/w p in c on f igura t ion operating junction temperature ( note 3) lt 83 30 e, lt 8330 i ............................. C 40 c to 125 c lt 83 30h ............................................ C 40 c to 150 c storage temperature range .................. C 65 c to 150 c (http://www .linear.com/product/LT8330#orderinfo) lt 8330 8330fa
3 for more information www.linear.com/LT8330 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 12v unless otherwise noted. parameter conditions min typ max units v in operating voltage range l 3 40 v v in quiescent current at shutdown v en/uvlo = 0.2v l 0.9 2 2 5 a a v en/uvlo = 1.5v l 2 3.6 5 9.5 a a v in quiescent current sleep mode, not switching l 5.5 8.5 10 15 a a active mode, not switching l 780 840 1100 1200 a a fbx regulation fbx regulation voltage fbx > 0v fbx < 0v l l 1.568 C0.820 1.6 C0.80 1.632 C0.780 v v fbx line regulation fbx > 0v, 3v < v in < 40v fbx < 0v, 3v < v in < 40v 0.005 0.005 0.015 0.015 %/v %/v fbx pin current fbx = 1.6v, C0.8v l C10 10 na oscillator switching frequency (f osc ) v in = 24v l 1.85 2.0 2.15 mhz minimum on-time v in = 24v 65 105 ns minimum off-time v in = 24v 47 65 ns switch maximum switch current limit threshold l 1.0 1.2 1.4 a switch r ds(on) i sw = 0.5a 330 m switch leakage current v sw = 60v 0.1 1 a en/uvlo logic en/uvlo pin threshold (rising) start switching l 1.620 1.68 1.745 v en/uvlo pin threshold (falling) stop switching l 1.556 1.60 1.644 v en/uvlo pin current v en/uvlo = 1.6v l C40 40 na soft-start soft-start time v in = 24v 1 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: intv cc cannot be externally driven. no additional components or loading is allowed on this pin. note 3: the LT8330e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT8330i is guaranteed over the full C40c to 125c operating junction temperature range. the LT8330h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 4: the ic includes overtemperature protection that is intended to protect the device during overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature will reduce lifetime. lt 8330 8330fa
4 for more information www.linear.com/LT8330 typical p er f or m ance c harac t eris t ics switching frequency vs temperature switching frequency vs v in normalized switching frequency vs fbx voltage switch current limit vs duty cycle switch minimum on-time vs temperature switch minimum off-time vs temperature fbx positive regulation voltage vs temperature fbx negative regulation voltage vs temperature en/uvlo pin thresholds vs temperature lt 8330 8330fa 100 50 75 100 125 normalized switching frequency (%) 8330 g06 v in = 12v duty cycle (%) 0 20 125 40 60 80 100 1.00 1.10 1.20 1.30 1.40 switch current limit (a) 150 8330 g07 v in = 24v junction temperature (c) ?50 ?25 0 25 50 75 100 175 125 150 175 30 40 50 60 70 80 90 1.570 100 minimum on?time (ns) 8330 g08 v in = 24v junction temperature (c) ?50 ?25 0 25 50 1.580 75 100 125 150 175 30 35 40 45 50 1.590 55 60 minimum off?time (ns) 8330 g09 v in = 12v en/uvlo rising (turn-on) en/uvlo falling (turn-off) junction temperature (c) ?50 ?25 1.600 0 25 50 75 100 125 150 175 1.54 1.56 1.610 1.58 1.60 1.62 1.64 1.66 1.68 1.70 1.72 1.74 en/uvlo pin voltage (v) 1.620 8330 g03 v in = 12v 1.630 fbx voltage (v) 8330 g01 v in = 12v junction temperature (c) ?50 ?25 0 25 50 junction temperature (c) 75 100 125 150 175 ?0.815 ?0.810 ?0.805 ?0.800 ?0.795 ?50 ?0.790 ?0.785 fbx voltage (v) 8330 g02 v in = 24v junction temperature (c) ?50 ?25 0 25 ?25 50 75 100 125 150 175 1.90 1.92 1.94 1.96 0 1.98 2.00 2.02 2.04 2.06 2.08 2.10 switching frequency (mhz) 8330 g04 v in (v) 25 0 5 10 15 20 25 30 35 40 45 50 1.85 1.90 1.95 2.00 2.05 2.10 2.15 switching frequency (mhz) 8330 g05 v in = 24v 75 fbx voltage (v) ?0.8 ?0.4 0.0 0.4 0.8 1.2 1.6 0 25
5 for more information www.linear.com/LT8330 typical p er f or m ance c harac t eris t ics switching waveforms (in ccm) switching waveforms (in dcm/light burst mode) switching waveforms (in deep burst mode) v out transient response: load current transients from 67.5ma to 135ma to 67.5ma v in pin current (sleep mode, not switching) vs temperature v in pin current (active mode, not switching) vs temperature burst frequency vs load current v out transient response: load current transients from 5ma to 135ma to 5ma lt 8330 8330fa 100 500mv/div i l 100ma/div 8330 g17 125 150 175 0 1.25 2.50 3.75 5.00 6.25 v in = 12v 7.50 8.75 10.00 v in pin current (a) 8330 g10 v in = 12v junction temperature (c) ?50 ?25 0 junction temperature (c) 25 50 75 100 125 150 175 600 650 700 ?50 750 800 850 900 950 1000 v in pin current (a) 8330 g11 v in = 12v v out = 48v ?25 front page application load current (ma) 0 10 20 30 40 50 0 0.5 0 1.0 1.5 2.0 2.5 switching frequency (mhz) 8330 g12 v in = 12v, v out = 48v, i load = 135ma 1s/div front page application v sw 25 20v/div i l 500ma/div 8330 g13 v in = 12v, v out = 48v, i load = 20ma 1s/div front page application v sw 20v/div 8330 g14 i l 500ma/div 50 v in = 12v, v out = 48v, i load = 2ma 1s/div front page application v sw 20v/div 8330 g15 i l 500ma/div front page application v in = 12v v out = 48v 75 100s/div v out 500mv/div i l 100ma/div 8330 g16 front page application v in = 12v v out = 48v 100s/div v out
6 for more information www.linear.com/LT8330 p in func t ions en/uvlo: shutdown and undervoltage detect pin . the LT8330 is shut down when this pin is low and active when this pin is high. below an accurate 1.6v threshold the part enters undervoltage lockout and stops switching . this allows an undervoltage lockout (uvlo) threshold to be programmed for system input voltage by resistively dividing down system input voltage to the en/uvlo pin. an 80 mv pin hysteresis ensures part switching resumes when the pin exceeds 1.68v. en/uvlo pin voltage below 0.2v reduces v in current below 1a. if shutdown and uvlo features are not required, the pin can be tied directly to system input. fbx: voltage regulation feedback pin for positive or negative outputs. connect this pin to a resistor divider between the output and gnd. fbx reduces the switching frequency during start-up and fault conditions when fbx is close to gnd. gnd: ground connection for the LT8330. the dfn pack - age has the best thermal performance due to an exposed pad ( pin 9) on the bottom of the package. this exposed pad must be soldered to a ground plane. pin 5 of the dfn package ( and pin 2 of the tsot package) should also be connected to a ground plane. the ground plane should be connected to large copper layers to spread heat dissipated by the LT8330. intv cc : regulated 3v supply for internal loads. the intv cc pin must be bypassed with a minimum 1 f low esr ceramic capacitor to ground. no additional components or loading is allowed on this pin. nc: no internal connection. tie directly to local ground. sw: the output of internal power switch. minimize the metal trace area connected to this pin to reduce emi. v in : input supply. this pin must be locally bypassed. be sure to place the positive terminal of the input capacitor as close as possible to the v in pin , and the negative terminal as close as possible to the gnd pin. lt 8330 8330fa
7 for more information www.linear.com/LT8330 b lock diagra m gnd 8330 bd + ? + ? error amp select frequency foldback intv cc uvlo oscillator 2mhz switch logic burst detect a5 a2 a1 error amp error amp slope vc slope soft-start 1.6v fbx v out r2 r1 ?0.8v uvlo ? + ? + a3 + ? a4 driver m1 i limit r sense pwm comparator intv cc t j > 170c + ? a6 1.68v(+) 1.6v(?) en/uvlo internal reference uvlo v in c in sw r4 opt r3 opt v in c out c vcc d l v out uvlo 3v regulator m2 lt 8330 8330fa
8 for more information www.linear.com/LT8330 o pera t ion the LT8330 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. op - eration can be best understood by referring to the block diagram . an internal 2mhz oscillator turns on the internal power switch at the beginning of each clock cycle. current in the inductor then increases until the current comparator trips and turns off the power switch . the peak inductor current at which the switch turns off is controlled by the voltage on the internal vc node . the error amplifier servos the vc node by comparing the voltage on the fbx pin with an internal reference voltage (1.60v or C0.80v, depending on the chosen topology ). when the load current increases it causes a reduction in the fbx pin voltage relative to the internal reference. this causes the error amplifier to increase the vc voltage until the new load current is satis - fied. in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation . the LT8330 is capable of generating either a positive or negative output voltage with a single fbx pin. it can be configured as a boost or sepic converter to generate a positive output voltage, or as an inverting converter to generate a negative output voltage. when configured as a boost converter, as shown in the block diagram, the fbx pin is pulled up to the internal bias voltage of 1.60v by a voltage divider (r1 and r2) connected from v out to gnd. amplifier a2 becomes inactive and amplifier a1 performs (inverting) amplification from fbx to vc. when the LT8330 is in an inverting configuration, the fbx pin is pulled down to C0.80v by a voltage divider from v out to gnd. amplifier a1 becomes inactive and amplifier a2 performs (non-inverting) amplification from fbx to vc. if the en/uvlo pin voltage is below 1.6v, the LT8330 enters undervoltage lockout (uvlo), and stops switching. when the en/uvlo pin voltage is above 1.68v (typical), the LT8330 resumes switching. if the en/uvlo pin volt - age is below 0.2v, the LT8330 only draws 1a from v in . to optimize efficiency at light loads , the LT8330 operates in burst mode operation in light load situations . between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input supply current to 6a. a chieving u l tralow q uiescent c urrent t o enhance efficiency at light loads the LT8330 uses a low ripple burst mode architecture . this keeps the output capacitor charged to the desired output voltage while minimizing the input quiescent current and output ripple. in burst mode operation the LT8330 delivers single small pulses of current to the output capacitor followed by sleep periods where the output power is supplied by the output capacitor. while in sleep mode the LT8330 consumes only 6a. as the output load decreases, the frequency of single cur - rent pulses decreases (see figure 1) and the percentage of time the LT8330 is in sleep mode increases, resulting in much higher light load efficiency than for typical con - verters. to optimize the quiescent current performance at light loads, the current in the feedback resistor divider must be minimized as it appears to the output as load current. in addition, all possible leakage currents from figure 1. burst frequency vs load current a pplica t ions i n f or m a t ion the output should also be minimized as they all add to the equivalent output load. the largest contributor to leakage current can be due to the reverse biased leakage of the schottky diode (see diode selection in the applications information section). lt 8330 8330fa 40 50 0 0.5 1.0 1.5 2.0 2.5 switching frequency (mhz) 8330 f01 v in = 12v v out = 48v front page application load current (ma) 0 10 20 30
9 for more information www.linear.com/LT8330 a pplica t ions i n f or m a t ion while in burst mode operation the current limit of the switch is approximately 240ma resulting in the output voltage ripple shown in figure 2. increasing the output capacitance will decrease the output ripple proportionally . as the output load ramps upward from zero the switch - ing frequency will increase but only up to the fixed 2mhz defined by the internal oscillator as shown in figure 1. the output load at which the LT8330 reaches the fixed 2mhz frequency varies based on input voltage, output voltage, and inductor choice. figure 2. burst mode operation p rogramming i nput t urn -o n and t urn -o ff t hresholds with en/uvlo p in the en /uvlo pin voltage controls whether the LT8330 is enabled or is in a shutdown state. a 1.6v reference and a comparator a6 with built-in hysteresis ( typical 80mv ) allow the user to accurately program the system input voltage at which the ic turns on and off (see the block diagram). the typical input falling and rising threshold voltages can be calculated by the following equations: v in(falling,uvlo(C)) = 1.60 ? (r3+r4)/r4 v in(rising, uvlo(+)) = 1.68 ? (r3+r4)/r4 v in current is reduced below 1a when the en/uvlo pin voltage is less than 0.2v. the en/uvlo pin can be con - nected directly to the input supply v in for always-enabled operation. a logic input can also control the en/uvlo pin. when operating in burst mode operation for light load currents, the current through the r3 and r4 network can easily be greater than the supply current consumed by the LT8330. therefore, r3 and r4 should be large enough to minimize their effect on efficiency at light loads. intv cc r egulator a low dropout (ldo) linear regulator, supplied from v in , produces a 3 v supply at the intv cc pin. a minimum 1f low esr ceramic capacitor must be used to bypass the intv cc pin to ground to supply the high transient currents required by the internal power mosfet gate driver. no additional components or loading is allowed on this pin. the intv cc rising threshold (to allow soft start and switching) is typically 2.6v. the intv cc falling threshold (to stop switching and reset soft start) is typically 2.5v. d ut y c ycle c onsidera tion the LT8330 minimum on-time, minimum off-time and switching frequency (f osc ) define the allowable minimum and maximum duty cycles of the converter (see minimum on-time, minimum off-time , and switching frequency in the electrical characteristics table). minimum allowable duty cycle = minimum on-time (max) ? f osc(max) maximum allowable duty cycle = 1 C minimum off-time (max) ? f osc(max) the required switch duty cycle range for a boost converter operating in continuous conduction mode (ccm) can be calculated as: d min = 1C v in(max) /(v out + v d ) d max = 1C v in(min) /(v out + v d ) where v d is the diode forward voltage drop. if the above duty cycle calculations for a given application violate the minimum and/or maximum allowed duty cycles for the LT8330, operation in discontinuous conduction mode (dcm) might provide a solution. for the same v in and v out levels, operation in dcm does not demand as low a duty cycle as in ccm. dcm also allows higher duty cycle operation than ccm. the additional advantage of dcm is the removal of the limitations to inductor value and duty cycle required to avoid sub-harmonic oscillations and the right half plane zero (rhpz). while dcm provides these benefits, the trade-off is higher inductor peak current, lower available output power and reduced efficiency. lt 8330 8330fa 5s/div v out 5mv/div i l 200ma/div 8330 f02
10 for more information www.linear.com/LT8330 a pplica t ions i n f or m a t ion s etting the o utput v oltage the output voltage is programmed with a resistor divider from the output to the fbx pin. choose the resistor values for a positive output voltage according to: r1 = r2 ? (v out /1.60v C 1) choose the resistor values for a negative output voltage according to: r1 = r2 ? (|v out |/0.80v C 1) the locations of r1 and r2 are shown in the block dia - gram. 1% resistors are recommended to maintain output voltage accuracy. higher-value fbx divider resistors result in the lowest input quiescent current and highest light-load efficiency. fbx divider resistors r1 and r2 are usually in the range from 25k to 1m. most applications use a phase-lead capacitor from v out to fbx in combination with high-value fbx divider resistors (see compensation in the applications information section). s of t -s t art the LT8330 contains several features to limit peak switch currents and output voltage (v out ) overshoot during start-up or recovery from a fault condition . the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. the LT8330 addresses this mechanism with an internal soft-start function. as shown in the block diagram, the soft-start function controls the ramp of the power switch current by controlling the ramp of vc through m2. this allows the output capacitor to be charged gradually toward its final value while limiting the start-up peak currents. figure 3 shows the output voltage and supply current for the first page t ypical application. it can be seen that both the output voltage and supply current come up gradually. figure 3. soft-start waveforms intv cc undervoltage (intv cc < 2.5v) and/or thermal lockout (t j > 170c) will immediately prevent switching, will reset the internal soft-start function and will pull down vc. once all faults are removed, the LT8330 will soft-start vc and hence inductor peak current. f requency f oldback during start-up or fault conditions in which v out is very low, extremely small duty cycles may be required to maintain control of inductor peak current. the minimum on-time limitation of the power switch might prevent these low duty cycles from being achievable. in this scenario inductor current rise will exceed inductor current fall during each cycle, causing inductor current to walk up beyond the switch current limit. the LT8330 provides protection from this by folding back switching frequency whenever fbx pin is close to gnd ( low v out levels ). this frequency foldback provides a larger switch-off time, allowing inductor current to fall enough each cycle (see normalized switch - ing frequency vs fbx voltage in the typical performance characteristics section). t hermal l ockout if the LT8330 die temperature reaches 170c (typical), the part will stop switching and go into thermal lockout. when the die temperature has dropped by 5c (nominal), the part will resume switching with a soft-started inductor peak current. lt 8330 8330fa 500s/div i l 500ma/div v out 20v/div 8330 f03
11 for more information www.linear.com/LT8330 a pplica t ions i n f or m a t ion s witching f requency and i nductor s election the LT8330 switches at 2mhz, allowing small value induc - tors to be used. 0.68 h to 10h will usually suffice. choose an inductor that can handle at least 1.4a without saturating, and ensure that the inductor has a low dcr (copper-wire resistance) to minimize i 2 r power losses. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor only carries one-half of the total switch current. for better efficiency, use similar valued inductors with a larger volume. many different sizes and shapes are available from various manufacturers. choose a core material that has low losses at 2mhz, such as a ferrite core. the final value chosen for the inductor should not allow peak inductor currents to exceed 1a in steady state at maximum load . due to tolerances, be sure to ac - count for minimum possible inductance value, switching frequency and converter efficiency . table 1. inductor manufacturers sumida (847) 956-0666 www.sumida.com tdk (847) 803-6100 www.tdk.com murata (714) 852-2001 www.murata.com coilcraft (847) 639-6400 www.coilcraft.com wrth (605) 886-4385 www.we-online.com i nput c apacitor bypass the input of the LT8330 circuit with a ceramic ca - pacitor of x7r or x5r type placed as close as possible to the v in and gnd pins. y5 v types have poor performance over temperature and applied voltage, and should not be used. a 4.7f to 10f ceramic capacitor is adequate to bypass the LT8330 and will easily handle the ripple cur - rent. if the input power source has high impedance, or there is significant inductance due to long wires or cables , additional bulk capacitance may be necessar y. this can be provided with a low performance electrolytic capacitor . a precaution regarding the ceramic input capacitor con - cerns the maximum input voltage rating of the LT8330. a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped) tank cir - cuit. if the LT8330 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT8330s voltage rating. this situation is easily avoided (see application note 88). o utput c ap acitor and o utput r ipple low esr ( equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they are small and have extremely low esr. use x5r or x7r types. this choice will provide low output ripple and good transient response. a 4.7f to 15f output capacitor is sufficient for most applications , but systems with very low output currents may need only a 1f or 2.2f output capacitor. solid tantalum or os-con capacitor can be used, but they will occupy more board area than a ceramic and will have a higher esr. always use a capacitor with a sufficient voltage rating. c ompensa tion the LT8330 is internally compensated . the decision to use either low esr (ceramic) capacitors or the higher esr ( tantalum or os-con) capacitors, for the output capacitor, can affect the stability of the overall system. the esr of any capacitor, along with the capacitance itself, contributes a zero to the system. for the tantalum and os-con capacitors, this zero is located at a lower frequency due to the higher value of the esr, while the zero of a ceramic capacitor is at a much higher frequency and can generally be ignored. a phase lead zero can be intentionally introduced by placing a capacitor in parallel with the resistor between v out and fbx. by choosing the appropriate values for the resistor and capacitor, the zero frequency can be designed to improve the phase margin of the overall converter . the typical target value for the zero frequency is between 30khz to 60khz. a practical approach to compensation is to start with one of the circuits in this data sheet that is similar to your ap - plication. optimize performance by adjusting the output capacitor and / or the feed forward capacitor (connected across the feedback resistor from output to fbx pin). lt 8330 8330fa
12 for more information www.linear.com/LT8330 c eramic c apacitors ceramic capacitors are small , robust and have very low esr. however, ceramic capacitors can cause problems when used with the LT8330 due to their piezoelectric nature. when in burst mode operation, the LT8330s switching frequency depends on the load current, and at very light loads the LT8330 can excite the ceramic capacitor at audio frequencies, generating audible noise. since the LT8330 operates at a lower current limit during burst mode op - eration, the noise is typically very quiet to a casual ear. if this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. low noise ceramic capacitors are also available. table 2. ceramic capacitor manufacturers taiyo yuden (408) 573-4150 www.t-yuden.com avx (803) 448-9411 www.avxcorp.com murata (714) 852-2001 www.murata.com d iode s election a schottky diode is recommended for use with the LT8330 . low leakage schottky diodes are necessary when low figure 4. suggested layout C (a) thinsot, (b) dfn quiescent current is desired at low loads . the diode leakage appears as an equivalent load at the output and should be minimized. choose schottky diodes with sufficient reverse voltage ratings for the target applications. table 3. recommended schottky diodes part number average forward current (ma) reverse voltage (v) reverse current (a) manufacturer pmeg6010cej 1000 60 50 nxp pmeg6030ep 3000 60 200 nxp l ayout h ints the high speed operation of the LT8330 demands care - ful attention to board layout. careless layout will result in per formance degradation . figure 4a shows the recom - mended component placement for the thinsot package . figure 4 b shows the recommended component placement for the dfn package . note the vias under the exposed pad. these should connect to a local ground plane for better thermal performance. a pplica t ions i n f or m a t ion r3 r4 r1 r2 gnd c2 c3 (a) (b) l1 d1 c1 v out v out v in 8330 f04a 8330 f04b fb c2 1 2 3 6 5 4 (v in ) r2 r4 r1 gnd c3 l1 d1 v out v out c4 fb v in 1 2 3 4 8 7 6 5 c1 c2 r3 (v in ) lt 8330 8330fa
13 for more information www.linear.com/LT8330 a pplica t ions i n f or m a t ion t hermal c onsiderations care should be taken in the layout of the pcb to ensure good heat sinking of the LT8330. the dfn package has the best thermal performance due to an exposed pad (pin 9) on the bottom of the package. this exposed pad must be soldered to a ground plane. pin 5 of the dfn package (and pin 2 of the tsot package) should also be connected to a ground plane. the ground plane should be connected to large copper layers to spread heat dissipated by the LT8330 and to further reduce the thermal resistance ( ja ) values listed in the pin configuration section. power dissipation within the LT8330 (p diss_LT8330 ) can be estimated by subtracting the inductor and schottky diode power losses from the total power losses calculated in an efficiency measurement. the junction temperature of LT8330 can then be estimated by, t j (LT8330) = t a + ja ? p diss_LT8330 a dditional t opologies : sepic and i nverting in addition to the boost topology, the LT8330 can be configured in a sepic or inverting topology . sepic and inverting converters are analyzed below. sepic c onver ter a pplica tions the LT8330 can be configured as a sepic (single-ended primary inductance converter ), as shown in figure 5. this topology allows for the input to be higher , equal, or lower than the desired output voltage . the conversion ratio as a function of duty cycle is: v out + v d v in = d 1 ? d in continuous conduction mode (ccm). in a sepic converter , no dc path exists between the input and output . this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the cir cuit is in shutdown. sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ), the input voltage (v in ) and the diode forward voltage (v d ). the maximum duty cycle (d max ) occurs when the converter operates at the minimum input voltage: d max = v out + v d v in(min) + v out + v d conversely, the minimum duty cycle (d min ) occurs when the converter operates at the maximum input voltage: d min = v out + v d v in(max) + v out + v d be sure to check that d max and d min obey: d max < 1-minimum off-time (max) ? f osc(max) and d min > minimum on-time (max) ? f osc(max) where minimum off-time , minimum on-time and f osc are specified in the electrical characteristics table. sepic converter: the maximum output current capability and inductor selection as shown in figure 5, the sepic converter contains two inductors: l 1 and l2. l 1 and l2 can be independent, but can figure 5. LT8330 configured in a sepic topology lt 8330 8330fa LT8330 v in v cc int d1 c in c out c dc 8330 f05 l1 l2 v out v in sw fbx gnd en/uvlo
14 for more information www.linear.com/LT8330 also be wound on the same core , since identical voltages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max)(ave) = i in(max)(ave) = i o(max) ? d max 1 ? d max i l2(max)(ave) = i o(max) in a sepic converter, the switch current is equal to i l1 + i l2 when the power switch is on, therefore, the maximum average switch current is defined as: i sw(max)(ave) = i l1(max)(ave) + i l2(max)(ave) = i o(max) ? 1 1 ? d max and the peak switch current is: i sw(peak) = 1 + c 2 ? ? ? ? ? ? ? i o(max) ? 1 1 ? d max the constant c in the preceding equations represents the percentage peak-to-peak ripple current in the switch , relative to i sw(max)( ave ) , as shown in figure 6. then, the switch ripple current ?i sw can be calculated by: ? i sw = c ? i sw(max)( ave ) the inductor ripple currents ?i l1 and ?i l2 are identical: ? i l1 = ?i l2 = 0.5 ? ?i sw the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of ?i l requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of ?i l allows the use of low in - ductances, but results in higher input current ripple and greater core losses . it is recommended that c falls in the range of 0.2 to 0.6. due to the current limit of its internal power switch, the LT8330 should be used in a sepic converter whose maximum output current (i o(max) ) is less than the output current capability by a sufficient margin (10% or higher is recommended): i o(max) < (1 C d max ) ? (1a C 0.5 ? ?i sw ) ? (0.9) given an operating input voltage range, and having cho - sen ripple current in the inductor, the inductor value (l1 and l 2 are independent) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? ? i sw ? f osc ? d max for most sepic applications, the equal inductor values will fall in the range of 1h to 47h. by making l 1 = l 2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2l, due to mutual inductance: l = v in(min) ? i sw ? f osc ? d max this maintains the same ripple current and energy storage in the inductors. the peak inductor currents are: i l1(peak) = i l1(max) + 0.5 ? ?i l1 i l2(peak) = i l2(max) + 0.5 ? ?i l2 the maximum rms inductor currents are approximately equal to the maximum average inductor currents. a pplica t ions i n f or m a t ion figure 6. the switch current waveform of the sepic converter 8330 f06 ?i sw = ? i sw(max)(ave) i sw t dt s i sw(max)(ave) t s lt 8330 8330fa
15 for more information www.linear.com/LT8330 based on the preceding equations, the user should choose the inductors having sufficient saturation and rms cur - rent ratings. sepic converter : output diode selection t o maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable . the average forward current in normal operation is equal to the output current. it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max) ? v d where v d is diode s forward voltage drop, and the diode junction temperature is: t j = t a + p d ? r ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter . sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 5) should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . i nver ting c onver ter a pplica tions the LT8330 can be configured as a dual-inductor inverting topology, as shown in figure 7. the v out to v in ratio is: v out ? v d v in = ? d 1 ? d in continuous conduction mode (ccm). a pplica t ions i n f or m a t ion inverting converter: switch duty cycle and frequency for an inverting converter operating in ccm, the duty cycle of the main switch can be calculated based on the negative output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v d v out ? v d ? v in(min) conversely, the minimum duty cycle (d min ) occurs when the converter operates at the maximum input voltage : d min = v out ? v d v out ? v d ? v in(max) figure 7. a simplified inverting converter c dc v in c in l1 d1 c out v out 8330 f07 + gnd LT8330 sw l2 + ? + ? + lt 8330 8330fa
16 for more information www.linear.com/LT8330 be sure to check that d max and d min obey : d max < 1-minimum off-time (max) ? f osc(max) and d min > minimum on-time (max) ? f osc(max) where minimum off-time , minimum on-time and f osc are specified in the electrical characteristics table. inverting converter: inductor, output diode and input capacitor selections the selections of the inductor, output diode and input capacitor of an inverting converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections. inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost, flyback and sepic converters for similar output ripples . this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flowing through the esr and bulk capacitance of the output capacitor: ? v out(p C p) = ? i l2 ? esr cout + 1 8 ? f ? c out ? ? ? ? ? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. the esr can be minimized by using high quality x 5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt - age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) > 0.3 ? ?i l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 7) should be larger than the maximum input voltage minus the output voltage (negative voltage): v cdc > v in(max) C v out c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? d max 1 ? d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . a pplica t ions i n f or m a t ion lt 8330 8330fa
17 for more information www.linear.com/LT8330 typical a pplica t ions 48v boost converter 8v to 16v input, 24v boost converter 3v to 6v input, 48v boost converter efficiency efficiency efficiency lt 8330 8330fa LT8330 8330 ta02b boost : v out = 24v v in = 8v v in = 12v v in = 16v load current (ma) 0 100 200 300 v cc 400 500 50 60 70 80 90 100 efficiency (%) 8330 ta03b int boost : v out = 48v v in = 3v v in = 5v v c1 in = 6v load current (ma) 0 2 4 6 8 10 12 c2 14 16 0 10 20 30 40 50 60 70 c3 4.7f 80 90 100 efficiency (%) 8330 ta04b c4 r1 1m r2 34.8k l1 6.8h 4.7f d1 d1: nxp pmeg6010cej l1: wrth we-mapi 3015 74438335068 c3: murata grm32er71h475k 8330 ta02 v in 12v v out 48v 135ma 71.5k 4.7f 1f v out 1f v in sw fbx gnd en/uvlo LT8330 8v to 16v v in 24v v cc 4.7pf int 1m l1 6.8h d1 c1 c2 c3 4.7f d1: diodes inc. sbr140s3 l1: wrth we-mapi 3015 74438335068 c3: murata grm32er71h475k c4 4.7pf v in r3 1m r4 287k r1 r2 210ma at v in = 8v 320ma at v in = 12v 450ma at v in = 16v 8330 ta03 4.7f 4.7f sw v out v in sw fbx gnd en/uvlo LT8330 3v to 6v v in 48v fbx v cc int l1 0.68h d1 c1 c2 1f c3 d1: nxp pmeg6010cej l1: wrth we-mapi 3012 744383340068 c3: murata grm32er71h475k r1 1m gnd r2 34.8k 12ma at v in = 3v 13ma at v in = 5v 14ma at v in = 6v 8330 ta04 v in = 12v boost: v out = 48v load current (ma) 0 40 en/uvlo 80 120 160 50 60 70 80 90 100 efficiency (%)
18 for more information www.linear.com/LT8330 typical a pplica t ions 3v to 6v input, 24v boost converter 8v to 30v input, 24v sepic converter efficiency efficiency lt 8330 8330fa LT8330 v in = 30v load current (ma) 0 60 120 180 240 300 50 60 3v to 6v 70 80 90 100 efficiency (%) 8330 ta06b v in 24v v cc int 1m l1 0.68h d1 c2 71.5k c3 4.7f c1 4.7f d1: nxp pmeg6010cej l1: wrth we-mapi 3012 744383340068 c3: murata grm32er71h475k r1 r2 30ma at v in = 3v 34ma at v in = 5v 35ma at v in = 6v 8330 ta05 1f 4.7f 71.5k 4.7f 1f 4.7pf c5 1f l2 6.8h 1m 287k v out v out v in sw fbx gnd en/uvlo LT8330 8v to 30v l1 6.8h v in 24v v in v cc int 1m d1 c1 c2 c3 d1: nxp pmeg6010cej l1: wrth we-tdc 8038 74489440068 c3: murata grm32er71h475k r1 sw r2 2 c4 r3 r4 160ma at v in = 8v 200ma at v in = 12v 250ma at v in = 24v 250ma at v in = 30v 8330 ta06 fbx boost : v out = 24v v in = 3v v in = 5v v in = 6v load current (ma) 0 4 8 12 16 gnd 20 24 28 32 36 40 30 40 50 60 en/uvlo 70 80 90 100 efficiency (%) 8330 ta05b sepic: v out = 24v v in = 8v v in = 12v v in = 24v
19 for more information www.linear.com/LT8330 typical a pplica t ions 4v to 36v input, 12v sepic converter 4v to 16v input, 5v sepic converter efficiency efficiency lt 8330 8330fa v out v in = 16v sepic: v out = 5v load current (ma) 0 80 160 240 320 400 50 v in 60 70 80 90 100 efficiency (%) 8330 ta08b sw fbx gnd en/uvlo LT8330 4v to 36v v in 12v 4.7f v cc int 1m d1 c1 c2 c3 d1: nxp pmeg6010cej l1: wrth we-tdc 8038 74489440047 c3: murata grm31cr61c475k r1 154k r2 2 c4 r3 1m r4 806k 170ma at v in = 4v 270ma at v in = 12v 280ma at v in = 24v 280ma at v in = 36v 8330 ta07 4.7f 4.7f 464k 4.7f 1f 4.7pf c5 1f l1 2.7h l2 2.7h v out v in 1f sw fbx gnd en/uvlo LT8330 4v to 16v v in 5v v cc int 4.7pf 1m d1 c1 c2 c3 d1: nxp pmeg6010cej l1: wrth we-tdc 8018 74489430027 c3: murata grm21br71c475k r1 r2 c4 c5 1f r3 1m r4 806k 280ma at v in = 4v 300ma at v in = 5v 380ma at v in = 12v 380ma at v in = 16v 8330 ta08 sepic: v out = 12v v in = 4v v in = 12v l1 4.7h v in = 24v v in = 36v load current (ma) 0 60 120 180 240 300 50 l2 4.7h 60 70 80 90 100 efficiency (%) 8330 ta07b v in = 4v v in = 5v v in = 12v
20 for more information www.linear.com/LT8330 typical a pplica t ions 8v to 30v input, C24v inverting converter 4v to 36v input, C12v inverting converter 4v to 16v input, C5v inverting converter efficiency efficiency efficiency lt 8330 8330fa v out int 1m d1 c1 c2 c3 4.7f d1: nxp pmeg6010cej l1: wrth we-tdc 8018 74489430027 c3: murata grm21br71c475k r1 r2 v in c4 r3 r4 280ma at v in = 4v 300ma at v in = 5v 380ma at v in = 12v 380ma at v in = 16v 8330 ta11 inverting: v out = ?24v v in = 8v sw v in = 12v v in = 24v v in = 30v load current (ma) 0 60 120 180 240 300 fbx 50 60 70 80 90 100 efficiency (%) 8330 ta09b inverting : v out = ?12v v in =4v gnd v in =12v v in =24v v in =36v load current (ma) 0 60 120 180 240 300 en/uvlo 50 60 70 80 90 100 efficiency (%) 8330 ta10b inverting: v out = ?5v v in = 4v LT8330 v in = 5v v in = 12v v in = 16v load current (ma) 0 80 160 240 320 400 8v to 30v 50 60 70 80 90 100 efficiency (%) 8330 ta11b v in ?24v 2.2f v cc int 1m d1 c1 c2 c3 d1: nxp pmeg6010cej l1: wrth we-tdc 8038 74489440068 c3: murata grm32er71h475k r1 34.8k r2 c4 r3 r4 l2 6.8h l1 6.8h 160ma at v in = 8v 200ma at v in = 12v 250ma at v in = 24v 250ma at v in = 30v 4.7f 8330 ta09 4.7f 71.5k 4.7f 1f 4.7pf c5 1f 1m 806k v out 1f v in sw fbx gnd en/uvlo LT8330 4v to 36v v in ?12v v cc 4.7pf int 1m d1 c1 c2 c3 d1: nxp pmeg6010cej l1: coilcraft lpd5030-472mr c3: murata grm21br71c475k r1 r2 c5 1f c4 r3 r4 l2 4.7h l1 4.7h 170ma at v in = 4v 270ma at v in = 12v 280ma at v in = 24v 280ma at v in = 36v 8330 ta10 1m 191k 4.7f 1f 4.7pf c5 1f l1 2.7h l2 2.7h 1m 806k v out 287k v in sw fbx gnd en/uvlo LT8330 4v to 16v v in ?5v v cc
21 for more information www.linear.com/LT8330 p ackage descrip t ion ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) please refer to http://www .linear.com/product/LT8330#packaging for the most recent package drawings. lt 8330 8330fa
22 for more information www.linear.com/LT8330 p ackage descrip t ion s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) please refer to http://www .linear.com/product/LT8330#packaging for the most recent package drawings. lt 8330 8330fa
23 for more information www.linear.com/LT8330 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . r evision h is t ory rev date description page number a 03/16 corrected v in quiescent current corrected typographic errors 3 2, 22, 23 lt 8330 8330fa
24 for more information www.linear.com/LT8330 ? linear technology corporation 2015 lt 0316 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LT8330 r ela t e d p ar t s typical a pplica t ion 8v to 40v input, 15v converter part number description comments lt1930/lt1930a 1a (i sw ), 1.2mhz/2.2mhz high efficiency step-up dc/dc converter v in = 2.6v to 16v, v out(max) = 34v, i q = 4.2ma/5.5ma, i sd < 1a, thinsot package lt 1935 2a (i sw ), 40v, 1.2mhz high efficiency step-up dc/dc converter v in = 2.3v to 16v, v out(max) = 38v, i q = 3ma, i sd < 1a, thinsot package lt 3467 1.1a (i sw ), 1.3mhz high efficiency step-up dc/dc converter v in = 2.4v to 16v, v out(max) = 40v, i q = 1.2ma, i sd < 1a, thinsot, 2mm 3mm dfn packages lt 3580 2a (i sw ), 42v, 2.5mhz, high efficiency step-up dc/dc converter v in = 2.5v to 32v, v out(max) = 42v, i q = 1ma, i sd = <1a, 3mm 3mm dfn-8, msop-8e lt 8494 70v, 2a boost/sepic 1.5mhz high efficiency step-up dc/dc converter v in = 1v to 60v (2.5v to 32v start-up), v out(max) = 70v, i q = 3a (burst mode operation), i sd = <1a, 20-lead tssop lt8570/lt8570-1 65v, 500ma/250ma boost/inverting dc/dc converter v in(min) = 2.55v, v in(max) = 40v, v out(max) = 60v, i q = 1.2ma, i sd = <1ma, 3mm 3mm dfn-8, msop-8e lt8580 1a (i sw ), 65v 1.5mhz, high efficiency step-up dc/dc converter v in : 2.55v to 40v, v out(max) = 65v, i q = 1.2ma, i sd = <1a, 3mm 3mm dfn-8, msop-8e efficiency lt 8330 8330fa sw fbx gnd en/uvlo LT8330 8v to 40v v in ?15v v cc int 4.7f 1m d1 c1 c2 c3 d1, d2: nxp pmeg6010cej l1a, l1b, l1c: coiltronics vp4-0075 c3, c4: murata grm32er71h475k r1 r2 r3 1m 56.2k r4 287k c4 4.7f +v out +15v d2 l1c 6h l1b 6h l1a 6h load 120ma at v in = 8v 4.7f 160ma at v in = 24v 170ma at v in = 40v 8330 ta12 ?v out = ?15v v in = 8v v in = 24v v in = 40v +v out = +15v load current (ma) 0 1f 40 80 120 160 200 50 60 70 80 90 c6 1f 100 efficiency (%) 8330 ta12b c5 1f ?v out v in

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